Integer Arithmetic Logic Unit

A comprehensive Verilog implementation of a scalable ALU system

This project demonstrates the design and implementation of a complete Arithmetic Logic Unit (ALU) supporting 12 operations across 4-bit, 8-bit, 16-bit, and 32-bit data paths. Built using Verilog HDL with comprehensive testing and waveform analysis.

12
Operations
4
Bit Widths
100%
Tested

ALU Operations

The ALU supports 12 distinct operations organized into three categories

Binary Logic Operations

¬

NOT

Bitwise inversion of operand A

Opcode: 0000
∧

AND

Bitwise AND of operands A and B

Opcode: 0001
⊼

NAND

Bitwise NAND of operands A and B

Opcode: 0010
∨

OR

Bitwise OR of operands A and B

Opcode: 0011
⊽

NOR

Bitwise NOR of operands A and B

Opcode: 0100
⊕

XOR

Bitwise XOR of operands A and B

Opcode: 0101
⊙

XNOR

Bitwise XNOR of operands A and B

Opcode: 0110

Arithmetic Operations

+

ADD

Addition: A + B + CI

Opcode: 0111
−

SUB

Subtraction: A - B - BI

Opcode: 1000
×

MUL

Multiplication: A × B

Opcode: 1001
÷

DIV

Division: A ÷ B

Opcode: 1010

Shift Operations

⇄

SHIFT

Arithmetic shift with configurable direction and amount

Opcode: 1011

ALU Control Modules

Scalable implementations from 4-bit to 32-bit data paths

4-Bit ALU

Educational

Foundation implementation demonstrating core ALU concepts

  • 4-bit operands and results
  • 8-bit multiplication output
  • Shifts: 0-3 positions
  • Range: 0-15

8-Bit ALU

Extended

Extended functionality for larger data processing

  • 8-bit operands and results
  • 16-bit multiplication output
  • Shifts: 0-7 positions
  • Range: 0-255

16-Bit ALU

Scalable

Mid-range implementation for enhanced capabilities

  • 16-bit operands and results
  • 32-bit multiplication output
  • Shifts: 0-15 positions
  • Range: 0-65,535

32-Bit ALU

Industry Standard

Full-scale implementation for modern processor architectures

  • 32-bit operands and results
  • 64-bit multiplication output
  • Shifts: 0-31 positions
  • Range: 0-4,294,967,295

ALU Architecture

Inputs
A[n:0]
B[n:0]
OPCODE[3:0]
CI, BI
ALU Control Module
Logic Ops Arithmetic Ops Shifter
Outputs
RESULT1[n:0]
RESULT2[n:0]
CO
OVERFLOW[n:0]

Waveform Analysis

Simulation results verified using Icarus Verilog and GTKWave

NOT Gate Waveform

4-Bit NOT Gate

AND Gate Waveform

4-Bit AND Gate

NAND Gate Waveform

4-Bit NAND Gate

OR Gate Waveform

4-Bit OR Gate

NOR Gate Waveform

4-Bit NOR Gate

XOR Gate Waveform

4-Bit XOR Gate

XNOR Gate Waveform

4-Bit XNOR Gate

Adder Waveform

4-Bit Adder

Subtractor Waveform

4-Bit Subtractor

Multiplier Waveform

4-Bit Multiplier

Divider Waveform

4-Bit Divider

Shifter Waveform

Arithmetic Shifter

4-Bit ALU Control Waveform

4-Bit ALU Control

8-Bit ALU Control Waveform

8-Bit ALU Control

16-Bit ALU Control Waveform

16-Bit ALU Control

32-Bit ALU Control Waveform

32-Bit ALU Control

About the Project

Project Overview

This project demonstrates the design and implementation of a complete Arithmetic Logic Unit (ALU) using Verilog HDL. The ALU integrates 12 distinct operations under unified control modules, demonstrating hierarchical design principles and comprehensive scalability from 4-bit to 32-bit data paths.

The implementation follows industry best practices for digital system design, including modular development, comprehensive testing, and waveform analysis. Each operation was individually verified before integration into the control modules.

Key Features

  • 12 integrated ALU operations (7 logic, 4 arithmetic, 1 shift)
  • Scalable design: 4-bit, 8-bit, 16-bit, and 32-bit implementations
  • Unified control interface with 4-bit opcode
  • Comprehensive testbenches for all operations
  • Waveform analysis using Icarus Verilog and GTKWave
  • Modular, hierarchical design approach

Author

Ibrahima Balde

Date: November 2025

Technology Stack

Verilog HDL
Icarus Verilog
GTKWave
Digital Design